Forum Discussion
Altera_Forum
Honored Contributor
9 years agoHi,
You get this warning because: Clock from PIN_R8 can directly feed only PLL_4, but you want to use PIN_R4 clock output which is dedicated clock output of PLL_1. So fitter puts your PLL in PLL_1 location to use dedicated clock output and routes clock from PIN_R8 trough GCLK (global clock network). So there is no way to avoid this warning in your case (unless you change your PLL mode to NORMAl and feed clock output trough ALTDDIO_OUT megafunction). I have worked with DE0-nano SDRAM and I have ignored this warning and SDRAM worked fine for me.