de0 nano output voltage probelm

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i have a de0 nano board

i have a design that consist of a number of components that are composed of multiple components (components inside components inside components).

the problem is that when a signal that must be generated from a low level component and advance to the output of the full design it comes out with half of the voltage that it must have in normal designs i.e(1.6v instead of 3.3v)

can any one help

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Your problem can not be due to the design hierarchy, you most likely have a driver conflict at the board-level. The difference between your designs is that one does not produce the driver conflict, while the hierarchical design does.

You can confirm that there is no problem with your design by first simulating it in Modelsim.

Another potential reason for reading an incorrect voltage with a voltmeter, is that rather than being a single logic level, you are some how probing a square wave. If you can probe with an oscilloscope, you can eliminate that as being the issue.

Cheers,

Dave

I'm actually new in fpga and i don't know how to use modesim in addition to that i don't know what you mean by driving conflict ........ can you explain please

and if there is another way to detect this conflict without using modelsim

thanks for helpping

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i don't know what you mean by driving conflict ........ can you explain please

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A driver conflict occurs when you connect two digital outputs together and configure one to drive high and the other to drive low.

The DE0-nano pins can be configured as both inputs and outputs. If you have added some wire to the header so that you can output on one pin, and then read-back the signal on another, then it is quite possible that you have accidentally created a driver conflict.

If you have not added any extra wires to the board, then this is not your problem.

How are you measuring the signal on the pin? With a voltmeter or an oscilloscope?

Cheers,

Dave