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SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

DDR4 calibration failed

Hi, I instantiate a EMIF IP core with DDR4 protocol in my design, modify memory timing parameters and board skew values. The DDR4 speed bin is 2400 and CL=16. After programming the device in EMIF ...
SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

thanks.

In my current design, maximum skew within DQ/DM/DQS is 7.3ps, but both "maximum board skew within address/command bus" and "average delay difference between address/command and CK" exceed ±20 ps, I think that violate the guidelines and results in calibration error, although no errors in "Report DDR".

Is there any way to solve this problem except hardware update?

thanks, regards.

BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi,

Basically we need to follow the board design guideline to get the calibration pass.

for now, I think you can try to reduce the frequency of the interface.