Forum Discussion
SYiwe
Occasional Contributor
Occasional ContributorDDR4 calibration failed
Hi, I instantiate a EMIF IP core with DDR4 protocol in my design, modify memory timing parameters and board skew values. The DDR4 speed bin is 2400 and CL=16. After programming the device in EMIF ...
BoonT_Intel
Frequent Contributor
Frequent Contributor- Check the DQ/DQS line length matching. Confirm is the board layout meeting the guideline.
- Try to reduce the interface frequency and retry. From the screenshot, looks like you are using 1066MhZ? Maybe reduce to 533Mhz.
- change the data line output and input impedance setting. - on FPGA IO tab.
SYiwethanks.
In my current design, maximum skew within DQ/DM/DQS is 7.3ps, but both "maximum board skew within address/command bus" and "average delay difference between address/command and CK" exceed ±20 ps, I think that violate the guidelines and results in calibration error, although no errors in "Report DDR".
Is there any way to solve this problem except hardware update?
thanks, regards.
- BoonT_Intel
Hi,
Basically we need to follow the board design guideline to get the calibration pass.
for now, I think you can try to reduce the frequency of the interface.
- BoonT_Intel
Hi, Perhaps you can give it a try by reduce the interface frequency (to 533MHz) and see the calibration results.
