Forum Discussion

SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

DDR4 calibration failed

Hi, I instantiate a EMIF IP core with DDR4 protocol in my design, modify memory timing parameters and board skew values. The DDR4 speed bin is 2400 and CL=16. After programming the device in EMIF ...
SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Thank you.

I can see three calibration stages in table 45: Address and command, Read, Write.

Does the three stages process as "Address and command" first, then "Read", and "Write" last?

Thanks, regards.