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SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

DDR4 calibration failed

Hi, I instantiate a EMIF IP core with DDR4 protocol in my design, modify memory timing parameters and board skew values. The DDR4 speed bin is 2400 and CL=16. After programming the device in EMIF ...
  • SYiwe's avatar
    SYiwe
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Thank you.

    Which of the following should I choose if my DDR4 SDRAMs and FPGA are soldered on the same borad: component, UDIMM, RDIMM or anything else?

    Regards.