DDR3 with HPC/Uniphy cores: what is the reason of the delays?

New question about the DDR3 controller (Half rate now).

Please see the picture.

http://f2.s.qip.ru/adnbvi8h.png

Refresh time interval is shown on it.

This is DDR3, Half rate, 667 Mhz.

The controller have inserted the refresh inside the bursts writing process.

Length of the bursts (on Avalon-MM) = 64, they are continuously filling the memory from avl_addr = 0 up to the end of the memory. No reads are performed (avl_readreq = 0 constantly).

The refresh is started by the PREA command (ddr3_addr = 0x0400, so A10 = 1).

After it is completed, the REFRESH command is issued.

This all is ok. But after the refresh command and Trfc time, the unexpected Read command to Bank 3 suddenly appears with PREA command after it.

I don’t understand, why it occurred and who requested this data (no external requests for it were performed).

But this Read command and PREA after it dramatically increases the time for refreshes (they became 3 times longer), so the bandwidth falls lower than the required value.

Is it possible to understand, what is this Read command origin and purpose?

Is it possible to remove it?

There is no described behavior with refreshes if the working frequency is 533 Mhz.

But if to work at 667, unpredicted Read operation appears.

This is RTL simulation.

Thank you in advance for answers.