Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

DDR3 with HPC/Uniphy cores: what is the reason of the delays?

Hello. I am trying to work with DDR3 on Stratix V. I've made a variation of DDR3 controller (HPC/Uniphy) and try to write there an information. When I choose the "Half rate" for the logi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thank you for answers.

I am working with the Stratix V Development Kit.

So, this is 64 bits of the memory + 8 bits for ECC.

--- Quote Start ---

If You're trying to write 16 bits data to 32bits chip running at half rate, then it's 64bits inside the controller, so You need to collect 4 packets to do such burst

--- Quote End ---

This could be a truth if avl_ready signal is active, but there is no data in my logic to send.

I have data, but can't send it to the DDR3 controller because avl_ready is inactive for a long time.