DDR3 with Cyclone 10 GX - Which Bank to use

Hi Sir,

For any given EMIF configuration, the pin-out of the EMIF-to-HPS interface is fixed. Banks and pins used for HPS access to a DDR interface are labeled HPS_DDR in the HPS Function column of the pin-out file. By default, the Intel FPGA that supported EMIF for HPS IP core together with the Intel Quartus Prime Fitter automatically implement the correct pin-out for HPS EMIF without user having to implement additional constraints. The supported Intel FPGA for HPS included Stratix 10 , Arria 10 , Agilex and etc.

Unfortunately, HPS is not supported for Cyclone 10 GX. So, you can freely use both I/O column 2 (Bank 2K/2J) and I/O column 3 (Bank 3A/3B) for EMIF placement. There is no difference in placing EMIF into both I/O column.

For more info, you can refer to section "6.3.3. Pin Guidelines for Intel Cyclone 10 GX EMIF IP" and section "6.3.3.1. General Guidelines" of this UG. It mentioned about certain requirements when placing the EMIF pins --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf

Hope this helps.

Thanks

Regards,

Aida