Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDDR3 Timings Violation - MAX10 NEEK
Hi there, I tried building a design example (downloaded from the altera cloud service) which is using the DDR3 UniPHY based memory controller. However, if compiled as it is without any changes ...
BDarji
Occasional Contributor
Occasional ContributorHello,
Although it is too late, this might be helpful to someone in future.
Answer given in following post helped us to close timing for DDR3 design on Max 10 development kit.
Thank you.
