Forum Discussion

Honored Contributor

9 years ago

DDR3 Timings Violation - MAX10 NEEK

Hi there, I tried building a design example (downloaded from the altera cloud service) which is using the DDR3 UniPHY based memory controller. However, if compiled as it is without any changes ...

BDarji

Occasional Contributor

5 years ago

Hello,

Although it is too late, this might be helpful to someone in future.

Answer given in following post helped us to close timing for DDR3 design on Max 10 development kit.

https://community.intel.com/t5/FPGA-Intellectual-Property/Recovery-violations-uniphy-DDR3/m-p/141584/highlight/true

Thank you.

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DDR3 Timings Violation - MAX10 NEEK

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