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Altera_Forum
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10 years ago

DDR3 Timings Violation - MAX10 NEEK

Hi there, I tried building a design example (downloaded from the altera cloud service) which is using the DDR3 UniPHY based memory controller. However, if compiled as it is without any changes ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I did a lot of experiments with the Quratus settings, however no result. I'll try to get deep in the qsys output and the generated memory module.

Galfonz, i'm not sure how the models of the physical device are implemented. Is there a way to set a specific temp for the simulations? From what I see in the qurtus settings I can only disable and enable the mulcticorner timing analysis (best/worst conditions).

Thanks for the replies.

Victor