DDR3 timing errors on Cyclone V

Hello,

Thanks for the attachment.

I've gone through it and below are my comments.

"The timing constraints for this core are broken."

I slightly disagree with this statement because of following reasons:

• The timing violation is occurs between the EMIF IP and other block designs as shown in the Report DDR. Therefore it's not in the core.
  • ; Core (Slow 1100mV 85C Model) ; Slow 1100mV 85C Model ; -3.392 ; 0.173 ;
• I created a design containing EMIF IP and run through the flow and there is no violation.
• Might be not accurate so if you can provide a small toy design that can replicate the issue, that will be good.

Since this timing issue occurred between EMIF IP and user logic/module, not in the core, a normal timing closure method is applicable. e.g. add pipeline register or set max delay constraint.