New Contributor
New ContributorThank you very much for your quick support.
Finally, by carefully analyzing the outer layer pattern to find the right position and using microscope to repeatedly check the drilling depth, I was able to drill 0.25mm hole and cut the wrong traces. They were cut close to the first DDR chip, so there are no stubs loading the line in the middle. Only some parts were left loading the FPGA output with undamped reflections. Next, I have connected vias under the FPGA and first DDR by a thin PTFE coax cable. Length was selected to match the PCB traces propagation. Shield was grounded to several vias close to the connection points.
Now it passes calibration and extensive tests @400MHz. So we can proceed with the V0 debugging before ordering next version.
It was a quite nasty mistake this time.
