KKomp
New Contributor
7 years agoDDR3 setup
Hello, I can't configure the HPS DDR3 memory on a custom board with the Cyclone V SoC. The memory is IS43TR16512A-125KBLI. The preloader stops in the rw_mgr_mem_calibrate_read_test_patterns function...
Please tell if there is any software trick to swap RAS/CAS pins (e.g. by FPGA lonaning, etc.). If there is no soft way, we will drill the board in a place where we can hit only the RAS and CAS lines and try to connect these on the through vias under the FPGA and DDR. This will affect signal integrity, but if we can run it at lower frequency we will be able to debug the board further before ordering the V1 version. Still there are some interfaces not checked, but this will be much easier if we can use the memory.