Forum Discussion

KKomp's avatar
KKomp
Icon for New Contributor rankNew Contributor
7 years ago

DDR3 setup

Hello, I can't configure the HPS DDR3 memory on a custom board with the Cyclone V SoC. The memory is IS43TR16512A-125KBLI. The preloader stops in the rw_mgr_mem_calibrate_read_test_patterns function...
KKomp's avatar
KKomp
Icon for New Contributor rankNew Contributor
7 years ago

Thank you for quick answers.

It is wrong fundamentally:/ After checking basic signal integrity I started looking at the command sequences and found that the DDR is not answering to any commands. Then I found that the RAS and CAS pins are swapped in the DDR schematic symbol:/

This would be very difficult to correct on the board and we may need to order corrected version as there is probably no option to swap these pins on the FPGA.