DDR3 setup

Hi KKomp,

Sorry, my mistake. Cyclone V FPGA HPS EMIF can't connect to normal FPGA GPIO. This can only be done with Arria 10 FPGA.

Your DDR3 calibration failed at guarantee read which is the first stage of calibration . So, most likely something fundamental is wrong here.

• https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/devices/cfg-index/calibration-checklist.html
• This link may gives you some clue on what's the potential cause of calibration failure

For you case, you need to go back to basic to review your DDR3 IP setting and manually check board schematic again.

For DDR3 IP setting review - pls ensure the DDR3 IP setting matched with DDR3 SDRAM datasheet spec

For board schematic review - focus on DDR3 power and connection review. You can leverage attached schematic review worksheet - DDR3 section to find out the exact power pin and DDR3 pin connection that you need to check

Thanks.

Regards

dlim