DDR3 setup

Thank you for quick hints. I have followed the idea to separate the board/IP config/preloader compilation issue. However I have found that I can't map the FPGA SDRAM controller IP core signals to the HPS SDRAM controller pins in the pin planner. Is there any way to do this? Or should I use the FPGA to HPS SDRAM bridge? Which side is responsible for the configuration and calibration if I use the bridge, not the purely FPGA based controller?