Forum Discussion

matif's avatar
matif
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

DDR3 SDRAM Examle Design state machine

module Avalon_bus_RW_Test ( iCLK, iRST_n, iBUTTON, local_init_done, avl_waitrequest_n, avl_address, avl_readdatavalid, avl...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi @matif​ ,

I am sorry for the delay in response due to current workload.

Let me clarify on DDR3 controller signal as below and hope it help for your understanding.

  • When "local_init_done” goes high, this indicate DDR3 calibration is completed and DDR3 controller is ready to accept user Avalon MM command. (user can send avalon command but controller won't process it yet)
  • User command will only be process once DDR3 avalon slave "avl_ready" goes high or its respective avalon master "wait_request" (this is normal wait_request signal without 'n') goes low .
  • So, yes you're right, the waitreq(n) is active low signal. Means that signal will be performing its function when its logic level is 0. So, there will be no data transaction (read/write , logic level is 0) during this period until the avl_ready goes high.

Hope this clear.

Thanks

Regards,

Aida

  • matif's avatar
    matif
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Dear Aida,

    Thank you so much for your reply. Is there any documentation of the above code? There are still some points that I need to understand. For example, in state 1 why is if (writecount[3]) is being used. It will be great if you can share some documentation of the above code.