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Altera_Forum's avatar
Altera_Forum
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10 years ago

DDR3 SDRAM controller core

I am working on Cyclone V project (5CEFA5F23C8) and I have DDR3 SDRAM controller core instantiated. I am getting hold violations for the DDR_DQ path. I have seen in the qsys that constraint script...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Nothing is automatically taken care of. DDR is highly dependent on board geometry. To the point that I just take the settings from example projects for the board in question. I don't have any experience in DDR design, it's a complex topic that I don't have time/desire to learn, or the expensive PCB software that would make it possible for a beginner to have any confidence in a DDR design.