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Altera_Forum
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10 years ago

DDR3 SDRAM controller core

I am working on Cyclone V project (5CEFA5F23C8) and I have DDR3 SDRAM controller core instantiated. I am getting hold violations for the DDR_DQ path. I have seen in the qsys that constraint script...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

In your top post you say "I have DDR3 SDRAM controller core instantiated" and in the lower post "I'm currently working on a board with no FPGA-based DDR" Which is it? In regards to the constraints, the tcl script adds them to the project when it's run. No sdc file is created.