DDR3 memory controller endianess

Hello,

I've implemented a Half Rate DDR3 controller on a Cyclone V FPGA.

There're 32 DQ lines - so the internal bus width is 128 bits (for WRITEDATA as well as READDATA).

The address width is 26 bits.

Now, because the DDR3 holds only 32 bits (and not 128) in each cell - the cell address is 28 (and not 26) bits wide.

So - when I issue a read command to binary address: 0b"0000_0000_0000_0000_0000_0000_00" the controller fetches back the values from cells:

0b"0000_0000_0000_0000_0000_0000_0000"

0b"0000_0000_0000_0000_0000_0000_0001"

0b"0000_0000_0000_0000_0000_0000_0010"

0b"0000_0000_0000_0000_0000_0000_0011"

My question is:

Suppose the DDR cells with the above address - hold the following data:

0b"0000_0000_0000_0000_0000_0000_0000" => 0x00000001

0b"0000_0000_0000_0000_0000_0000_0001" => 0x00000002

0b"0000_0000_0000_0000_0000_0000_0010" => 0x00000003

0b"0000_0000_0000_0000_0000_0000_0011" => 0x00000004

Assuming READDATA is defined as 127 downt to 0 (the leftmost bit is the LSB )- How will its content look like?

Will it be:

0x 00000001_00000002_00000003_00000004

or

0x 00000004_00000003_00000002_00000001

?