DDR3 interfacing with Cyclone V E device

The FPGA itself does not care about how much memory you're accessing. It depends on the board.

The only limitation I see is if you try to use it with a NIOS processor, which is 32-bit limited and uses the upper bit for non-cached access. And because the address space is shared with the other peripherals, effectively 1GB.

But you could split this 1GB into "banks" or perhaps chunk it to 8 other NIOS.

But the device itself can handle whatever.