DDR2 Read-Write-Read-Write Example

Hi Joe306,

The timing looks "twisted" because of the fact that when you are doing a write the controller needs the data right after the write command and for reads the data appears after the controller has read the data from the memory.

So, when you think about writes, then the controller would need to have the data to be written to memory just after it issues the actual "WRITE" command to memory. In order to have the data to be transferred to memory available for the transaction the controller will ask for the data from the user early enough (to be buffered internally etc.)

Reads work differently; the controller will first issue the "READ" command to the memory, after which it has to wait for a number of clock cycles for the controller to fetch the data from memory. Only after the data is read from the memory can the controller give the data to user, i.e. assert the local_rdata_valid. If you look carefully at the DDR SDRAM interface waveforms (especially ddr_dq and ddr_dqs) and the local_rdata_valid signal you can see that local_rdata_valid signal gets asserted right after the data is read from the memory.

I hope that makes sense..