ddr2 high performance ip core

Most memory modules have already two ranks or blocks of memory internally, they have basically separate chip selects and ODT signals, also at least two pairs of clock signals. The memory controller is controlling ODT in an appropriate way. However, different techniques have been suggested by memory manufacturers regarding optimal ODT control. The weak point with Altera memory controller and Cyclone II/III or Arria/Stratix II is, that no dynamic on-chip-termination at the FPGA side is present. This feature is starting with Stratix III.