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Altera_Forum
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17 years ago

ddr2 high performance ip core

i am designing PCI2DDR2 interface i want to use the ip core with CycIII device. does the core support ECC thats less then 64 bit? the PCI data is 32 bit i am going to interface 10 DDR2 compone...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The simple thing is, you can share the memory bus for two blocks of memory with separate chip selects. Assigning the 9 or 10 DQS groups to Cyclone III resources is more complicated . There are different combinations allowing different operating speeds, AN445 is specially describing Cyclone III DDR interface. Finally, I don't know details regarding ECC option.