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Altera_Forum
Honored Contributor
Honored Contributorddr2 high performance ip core
i am designing PCI2DDR2 interface i want to use the ip core with CycIII device. does the core support ECC thats less then 64 bit? the PCI data is 32 bit i am going to interface 10 DDR2 compone...
Altera_ForumHonored Contributor
Honored ContributorThe simple thing is, you can share the memory bus for two blocks of memory with separate chip selects. Assigning the 9 or 10 DQS groups to Cyclone III resources is more complicated . There are different combinations allowing different operating speeds, AN445 is specially describing Cyclone III DDR interface. Finally, I don't know details regarding ECC option.
