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Altera_Forum's avatar
Altera_Forum
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19 years ago

DDR2 Design with Cyclon III

Hi all I just started a new desing using a Cyclon III to interface discrete DDR2 memory (No DDR2 module!). It is just one single chip per interface. Can someone help me choosing the right...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

its not the speed of the bus that causes your problems, its the speed of the edges.

it is possible to select series termination on the address & ctrl lines as well as the data lines. just open up the assignments editor and add them manually.

select "output termination" for "assignment name", and then select whichever OP impedance you desire... I recommend 25R.

Have you tried any of the Altera Megafunctions?

You should do as Avatar suggested and simulate using Hyperlynx. better to be safe than sorry. all IBIS models can be downloaded from the Altera web site.

Hope this helps