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11 years agoDDR2 Altmemphy Read and write through Nios
I am using a DDR2 altmemphy controller IP for
Cyclone III FPGA EP3C120F780C7 DDR2 IC: MT47H32M8BP-3X1 for read/write application using nios-ii processor. QSYS Connections are as shown in the ddr2_qsys.xps file below. Included files. 1.ddr2_altmemphy.v top level file. 2.ddr2_altmemphy.qsf 3.ddr_altmemphy.out.sdc 4.altpll1.v 5.altpll1.qip 6.alt_ddr2.qsys 50MHz input clock 100MHz DDR2 altmemphy IP clock=PLL Reference Clock Memory Clock Frequency: 150 MHz Clarifications: 1. Is the Qsys system interconnection correct? 2.I have set DDR2 memory as both instruction and data memory, so when the processors compiles and executes the sample nios-ii application from bsp hello_world program it should display "Hello from Nios" in the nios-II console, but i am getting failed to download the elf error, what might be the reason? 3. How to write to the memory from the processor side, what is the command syntax? and what is the command syntax to read from the DDR2 memory? 4. What is the command from the processor side to control bank select ? Regards, Sriram