Honored Contributor
Honored ContributorI'm ****ing around with this driver at the moment so I'll give this one a shot...
The user guide says: "■ Incomplete write operation The state machine issues a series of write requests that are less than the maximum burst size supported by your controller variation. The addresses are then read back to ensure that the controller has issued the correct signals to the memory. This test is only applicable in full-rate mode, when the local burst size is two. You can skip this test by setting the test_incomplete_writes_on signal to logic zero. So in my system, the DDR that I am using supports burst sizes of 4 or 8 - I am running at 4. Since the interface is DDR - it latches data on both edges of the clock - the local bus size for the DDR controller is 2x the width of the DRAM. A local burst size of 2 reflects a ddr burst size of 4 or 2 complete DQS cycles What the test does is forces the DDR controller to drive the DM signals at thew appropriate time to mask the invalid piece of data from getting to the memory - the data transfer looks exactly the same as it would if the write was a complete burst, however the invalid write data is masked from being written to memory. As far as an address line test, if you are playing with an FPGA, you should be able to figure out how to test if your address pins are stuck low high or are open...
