Altera_ForumHonored Contributor15 years agoDDR SDRAM connection to FPGA Hi, I'm trying to design a board for EP3C16Q240C8N FPGA and MT46V16M16P DDR SDRAM. I have read some application notes which say that I have to connect SDRAM data lines to DQ/DQS blocks. My sele...Show More
Recent DiscussionsWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?System PLL of Agliex5 PCIE example design cannot be locked after configurationJTAG Chain Broken on Agilex 7-I Dev KitRequest for Cyclone V Pinout File InformationCyclone 10 LP's Extended Industrial parts