DDR Output Constraining - "too positive" slack

Thanks guys for the help!

I was able to fix the RGMII input without a PLL by inserting LCELLs but that is not a reliable solution. Quartus does not add such delays when simply constraining tSU/tH (gives up and reports negative slack), they have to be added manually and they can only meet fast or slow device... and the case here was that the system was unstable over time... Perhaps one can play with the delays for a single FPGA-PHY combination and find the "perfect" delay parameters, but for a larger volume with faster and slower FPGAs...

I gave up with RGMII, most likely will go with GMII PHYs.