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125MHz should work without a PLL...
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Are you sure? I made a small test and I couldn't meet timing.
Note that per RGMII specs, the clock must be delayed and center aligned. To comply with the specs without a PLL (and without enabling the PHY clock delay), I had to insert a bunch of LCELLS before the clock output. Then I could meet timing at either the slow or fast model, but not at both.
The main problem seems to be that the PVT variation of the LCELL delay-chain is too much. And the fact that he is using a Cyclone II without hardware DDIO support doesn't help. But it was a quick test, I might have missed something.
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