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Thanks for the reference, I already read this several times :-D but as I said, PLLs are not an option.
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You are misunderstanding my point. The
phy device can center-align the clock for you, at least most PHY have that capability. My point was that if you don't use a PLL to shift the clock, then you should enable the clock delay on the PHY. And that with none of them (no PLL shift in the FPGA, and no clock delay at the PHY), then meeting timing would be very difficult.
Regarding your exact TimeQuest issue, I think you are missing the multicycle exception statement (Rysc would correctly if I'm wrong). But again, constraints would be completely different with or without the PHY clock delay.
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