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dipling,
Check this:
http://www.altera.com/literature/an/an477.pdf As mentioned on that note, most PHY devices have an option to center-align the clock. Without a PLL to shift the clock at the FPGA, it would be very difficult to meet timing otherwise. This is valid both for the transmitter side and the receiver side (as in your other post).
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Thanks for the reference, I already read this several times :-D but as I said, PLLs are not an option. I will have a number of 8 phys connected to the FPGA and at most 2 available PLLs... besides, each tx clock will range between 2.5 and 125 mhz so... I am "constrained" to a maximum of 0 PLLs :-D
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