Honored Contributor
Honored ContributorIf your launch register is feeding two external registers, then the latter might have a lot of slack, which is fine. It's the tighter constraint that is th one you want analyzed. If this is the tighter path, than something seems incorrect, as there should be a path to the falling edge register with a requirement of 4.444ns.
I'm guessing your false paths are incorrect. For example, you have a false-path with "-setup -from rise_from -to fall_to", so in essence you're cutting the path I'm talking about. I would comment out/remove those false paths and try again. (Those false paths are usually for ignoring timing on the less restrictive paths, i.e. the launching edge has a setup requirement of 4.444ns to the falling edge register and 8.888ns to the rising edge one. The latter can be ignored, but it also doesn't hurt to leave it in, since you know if you meet timing to hte 4.444ns, you'll meet the 8.888ns requirement.) Finally, analyze what it's saying. When a clock comes into the FPGA, the clock delay to the source register is 3.592ns and the data delay out is 3.981ns, so it takes 7.573 to get the data out, while the clock takes 6.759ns. This is the "latest" the data could get out compared to the clock. You'll also need to analyze -hold to see the earliest it could get out. This at least should give you a better sense of what things look like.
