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Altera_Forum
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16 years ago

DDR Output Constraining - "too positive" slack

Hi, I hope someone knows the solution to the problem that kept me really busy lately :( I have to connect to an RGMII PHY that has the following parameters: tCLK = 8 (ns) TskewR (Da...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

dipling,

Check this: http://www.altera.com/literature/an/an477.pdf

As mentioned on that note, most PHY devices have an option to center-align the clock. Without a PLL to shift the clock at the FPGA, it would be very difficult to meet timing otherwise. This is valid both for the transmitter side and the receiver side (as in your other post).