DDR input Source synchronous center-aligned SDC

Hi guys!

https://www.alteraforum.com/forum/attachment.php?attachmentid=8147

How would you guys assign the SDC for DDR source-synchronous input for LCLK and Data?

Assume data is running on 500 Mhz DDR.

This is my opinion:

This is center aligned, opposite edge transfer, So#

create_clock -name virtual_clk -period 2 -waveform {0.5 1.5}

create_clock -name Lclk_P -period 2 [get_ports {Lclk_P}]#

Am I correct?

Many thanks!