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The data stream once latched by Bitclock at 480MHz is separated into 12 bit data using the slow 80MHz frame clock.
So Centre aligned input same/opposite edge capture should work.
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The 80MHz clk is irelevant to ddr interface. We are talking about io paths not 480 to 80 path
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Is there a way to simulate this? For some reason, my model-sim gate level simulation doesn't work. Says the design unit not found in library. I could run functional simulations properly using the same setup..
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check you have installed those libraries or try modelsim directly not through quartus launch. You can also try quartus simulator possibly older versions.
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