DDR Input Same Edge vs Opposite Edge transfer

The data stream once latched by Bitclock at 480MHz is separated into 12 bit data using the slow 80MHz frame clock.

So Centre aligned input same/opposite edge capture should work.

Is there a way to simulate this? For some reason, my model-sim gate level simulation doesn't work. Says the design unit not found in library. I could run functional simulations properly using the same setup..