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lidongyang
New Contributor
New ContributorDDR EMIF support 256bits data width for RDIMM x4?
Hi Intel, Do you know how to create EMIF using qsys that support for 2 AXI masters with different data widths (256bits and 512bits) on RDIMM x4?
lidongyangNew Contributor
New ContributorHi Adzim,
I think the question should be:
We are using an organization x4 (dqs x4) RDIMM but cannot access by 256bit axi because of the byte-enable does not support organization x4.
To describe it in more detail:
Organization x4 means in qsys "EMIF" configuration "Memory" page, there is an option:
DQ pins per DQS group is 4. (we cannot change this value to
when the above value is 4, "data mask" and "Read DBI" cannot be enable.
if "data mask" and "Read DBI" cannot be enable, the ctrl_amm0 bus won't have amm_byteenable.
if amm_byteenable is not there. EMIF can only be accessed by 512bits.
Do we have a way to configure organization x4 RDIMM for 256bit axi access?
