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Altera_Forum's avatar
Altera_Forum
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16 years ago

DCLK and DATA0 connected to LVDS output instead of floating

The Cyclone II handbook says that after programming, the DCLK and DATA0 inputs should not be left floating and should therefore be connected to a logic high or low. However, it also states that th...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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at least make sure FPGA LVDS buffers can drive 100 m UTP cable

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They surely can as long the cable is correctly terminated. The more interesting question is however, if the data can be received correctly at the other end. "Long distance" cable drivers are partly using preemphasis to precompensate for the cable losses, also the ability of a dedicated LVDS receiver to decode attenuated signals has been improved with some types.

Did you try a test setup with 100m CAT5 cable? The nominal CAT5 - CAT7 attenuation is 13 dB/100m @ 16 MHz and 18 dB @ 32 MHz, making it unlikely to operate a 32 MBPS LVDS link successfully without additional signal gain and an equalizer compensating the cable loss.