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One (curious) question: how many circuits are you going to build? Tens or thousands?
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A production run of 1000 to 4000 (depending on how well they perform).
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If you insert a 'live' RJ45 connector into its mating socket the sequence of making contact is undefined. Sometimes the Vcc makes and some signals make contact before the Gnd finally gets there. Some circuits do not survive this 'game of Russian roulette'.
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Good point. Part of this can be solved (in my case) by instructing the installer not to powerup the main unit until the remote unit has been plugged in.
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The termination could be the Achilles' Heel. The slow slew on the TTL outputs may not be enough to get rid of reflections on the Dclk and Data0. If it turns out to be enough they represent a significant resistance of 50 ohm (or more). These resistances in combination with the mandatory 100 ohm termination to receive LVDS later will eat heavily into the signal swing of the TTL outputs. To quote Einstein: "Everything should be made as simple as possible, but not simpler."
Do you need 32 MHz signalling rate towards FPGAremote?
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Well, I need 8MHz datarate, 32MHz is a tad bit higher than the minimum. So lowering that would still be an option (a bit).
However, I shopped around for some LVDS drivers/receivers, and eventually found: SN65LVDS391 and SN65LVDT390 from Texas Instruments. They offer >15kV ESD protection, which is significantly higher than the 1kV of the standard Cyclone II protection.
So what I'll do now is skip the LVDS on the FPGA and simply use LVTTL to/from the buffers. This automatically solves the DATA0/DCLK/nCONFIG issues, since I connect them over three pairs, through LVDS, through the buffers.
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