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One more observation is that at the end of the configuration of FPGAremote this may possibly start sending data on the LVDS outputs before you can tristate the TTL outputs on FPGA main, possibly disrupting the configuration.
Why not use 2 more wires between FPGAmain and FPGAremote?
Or use LVCMOS differential signalling instead of LVDS (saving 2 pins on FPGAmain as well)?
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Well, for one, I know exactly in FPGAmain when the config data is complete, so I can switch to tristate well before FPGAremote has finished its boot-process.
As for two more wires, yes, I wish...
The connection that I have between main and remote is a CAT-5 cable with 4 wirepairs.
One wirepair is used for GND/18V (the powerlines).
One wirepair is used for LVDS communication from FPGAmain to FPGAremote.
One wirepair is used for LVDS communication from FPGAremote to FPGAmain (and doubles as DCLK/DATA0 during the configuration stage).
One wire is used for nCONFIG to FPGAremote.
One wire is unused (but will probably be connected to GND).
So, in short, I don't have the two extra wires (I have one, but that doesn't solve the problem). Unless someone has a clever idea on how to solve this differently given the CAT5 constraint.
As for using LVCMOS hand-made differential signaling. That would be an option, I guess. But I'd like to communicate over CAT5 wires up to a 100m with 32MHz, so real LVDS would be better, I think.
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