Honored Contributor
Honored ContributorThe fifo is used for a MII communication (50 MHz input and 25 MHz output). For this particular project, I'm driving an ethernet PHY, so the wrclk is from the internal FPGA pll, and the rdclk is from the PHY. The fifo I mentioned is used for tx part, in which I have full control. First I write the message to this fifo, and after that I give the "send" command by writing the length of the message in a different fifo.
I have a solution for this problem, knowing what the first useful byte must be, I can reset manually the fifo, but I disagree with this solution because by doing this I miss a packet. :|
