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Altera_Forum's avatar
Altera_Forum
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17 years ago

DCFIFO read/write request control

Hi, I'm using dcfifo's in a design with the rdreq and wrreq signals. The clock on both sides of the fifo is the same frequency but it will be out of phase. When the fifo comes out of reset, sho...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

Altera always warns of such attempts. I will make sure that I got data on the read side before I read else things become unpredictable according to altera...

I am not sure if underflow protection will just stop that.

additionally, for dcfifo, it is safer to release reset synchronised to write clock.

kaz