Honored Contributor
Honored ContributorHi Jerry,
--- Quote Start --- We used AC couple for our system, but there is still DC inside FPGA after ADC sampling without any signal feeding, why? --- Quote End --- DC appears due to the asymmetries in the ADCs quantization transfer function. The conversion from analog voltage to a digital code is ideally a linear 'staircase' with each code converting an equivalent width of voltages. Practical ADCs have varying widths, and so some code bins end up with more samples than they really should, and others have less. The DC value of the digital signal it is mean, or expected value, and the expected value is <x> = sum_n w[n]P[n] where w[n] is the output weight (binary code) and P[n] is the probability of that code, i.e., the histogram bar height normalized by the number of samples. The histogram bar heights for a symmetric input, eg. a sine wave, have symmetry in the P[n], but when you have non-linear threshold voltages, the P[n] change heights, and this results in <x> having a non-zero value, i.e., a mean or DC offset. The attached document has a more detailed explanation. Look at the noise source figures, and you'll see DC created by the threshold non-linearities. Note that you will also get DC if you do your rounding wrong, i.e., if you use truncation. See the slides in this talk for an example of that (p41 of the PDF, p40 on the slide); http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf) Cheers, Dave
