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Altera_Forum
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14 years ago

DC offset removal using FPGA?

I am new to interface FPGAs with DSP concepts. I have ADCs and then i have deserializers after them to parallelize the data. So should i apply the DC removal after the deserializer or before it? ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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Do u mean that the tap delay which is infact the number of coefficients will be equal to the number of samples we have at the imput?

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For a simple implementation of an FIR filter with N taps, you will have N-1 registers that are clocked at the same rate as the ADC. You will have N-input samples from the ADC inside the delay line of the FIR filter (one at the input, and (N-1) in the registers) at any point in time.

So you will have an equal number of samples as coefficients inside the FPGA.

Cheers,

Dave