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Altera_Forum
Honored Contributor
Honored ContributorData type used in VHDL
Hi, I am newbie to VHDL design. I came across a question of using VHDL. I'd like to output a 17 bit data through one port (one pin in an Altera chip) to my DSP on the the same circuit bo...
Altera_ForumHonored Contributor
Honored ContributorHi, Ben,
Thank you for your advice. I will send one bit to the assigned pin every clk cycle. The clock signal is sent from DSP to Altera chip. I am trying to send my data from Altera to DSP through CAN bus... Again, I appreciate your help! -ecenus --- Quote Start --- Setting each data bit to be a std_logic output will use one pin for each data bit and is basically the same as a std_logic_vector with the same number of bits. If you want to send 17 bits to your dsp using one pin then you will need to set that output to each data bit one at a time. You will also want to think about sending a clock and a control signal so the dsp knows which bit it is receiving. --- Quote End ---
