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Altera_Forum
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17 years ago

Data type used in VHDL

Hi, I am newbie to VHDL design. I came across a question of using VHDL. I'd like to output a 17 bit data through one port (one pin in an Altera chip) to my DSP on the the same circuit bo...
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Altera_Forum
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17 years ago

Hi, Ben,

Thank you for your reply!

Can I set each bit of the data as STD_LOGIC as well?

Thanks, again!

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You need to serialise the 17 data bits and use a std_logic type. When using a std_logic_vector type as an ouput each bit will tie up with one pin on your device.

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