wire mm_bridge_2_s0_waitrequest;
wire mm_bridge_2_s0_readdata;
wire mm_bridge_2_s0_readdatavalid;
reg mm_bridge_2_s0_writedata=0;
reg mm_bridge_2_s0_address=0;
reg mm_bridge_2_s0_write=0;
reg mm_bridge_2_s0_read=0;
//reg mm_bridge_2_s0_read_requested=0;
//reg mm_bridge_2_s0_write_requested=0;
reg fifo_read_offset= 32'h20000000;
reg fifo_read_address=0;
reg fifo_write_offset=32'h28000000;
reg fifo_write_address=0;
if(!source_empty && !mm_bridge_2_s0_waitrequest)
begin
mm_bridge_2_s0_read<=1;
mm_bridge_2_s0_address<=fifo_read_offset|{5'b0,fifo_read_address};
fifo_read_address<=fifo_read_address+4;
source_empty<=...;
end
else if(!mm_bridge_2_s0_waitrequest)
mm_bridge_2_s0_read<=0;
if(mm_bridge_2_s0_readdatavalid && !core_full)
... <= mm_bridge_2_s0_readdata;
else
mm_bridge_2_s0_read<=0;
if(core_readdatavalid && !mm_bridge_2_s0_waitrequest)
begin
mm_bridge_2_s0_write<=1;
mm_bridge_2_s0_writedata <= ...;
mm_bridge_2_s0_address<=fifo_write_offset|{5'b0,fifo_write_address};
fifo_write_address<=fifo_write_address+4;
end
else if(!mm_bridge_2_s0_waitrequest)
mm_bridge_2_s0_write<=0;
....
// FPGA->HPS access wires
.mm_bridge_2_s0_waitrequest(mm_bridge_2_s0_waitrequest), // mm_bridge_1_s0.waitrequest
.mm_bridge_2_s0_readdata(mm_bridge_2_s0_readdata), // .readdata
.mm_bridge_2_s0_readdatavalid(mm_bridge_2_s0_readdatavalid), // .readdatavalid
.mm_bridge_2_s0_burstcount(1'b1), // .burstcount
.mm_bridge_2_s0_writedata(mm_bridge_2_s0_writedata), // .writedata
.mm_bridge_2_s0_address(mm_bridge_2_s0_address), // .address
.mm_bridge_2_s0_write(mm_bridge_2_s0_write), // .write
.mm_bridge_2_s0_read(mm_bridge_2_s0_read), // .read
.mm_bridge_2_s0_byteenable(4'hf), // .byteenable
.mm_bridge_2_s0_debugaccess(1'b0), // .debugaccess
Honored Contributor
