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Re: bandwidth, 2 GB/s would be only achievable with burst transfers. When writing one word at a time, it may be less (possibly much less). Not sure.
As in my first example, instantiate an altera_hps and an altera_avalon_mm_bridge. Connect bridge.m0 -> hps.f2h_axi_slave. Export bridge.s0. Now you have access to signals:
mm_bridge_0_s0_waitrequest
mm_bridge_0_s0_address
mm_bridge_0_s0_writedata
mm_bridge_0_s0_write
When you have data, you wait till 'waitrequest' is 0, put 1 into 'writedata', put your data into 'write', and put the physical address of RAM where you want to write into 'address'.
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Ok so I got that, now the channel width is only 128 Bits, would I write 128 Bits to the mm_bridge_0_s0_write multiple times advancing the physical RAM address by 128 each time? Or could I write the full say 37KBits into write data at once and the mm bridge will take care of the streaming? Sorry for my lack of knowledge on this, I really do appreciate the assistance
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